In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, a typical application of a charge pump circuit is the generation of a programming voltage V.sub.PP utilized to program data into memory cells in non-volatile electrically block-erasable or "FLASH" memories, as will be understood by those skilled in the art. A charge pump may also be utilized in a conventional dynamic random access memory ("DRAM"), to generate a boosted word line voltage V.sub.CCP having an amplitude greater than the amplitude of a positive supply voltage V.sub.CC or a negative substrate or back-bias voltage V.sub.bb that is applied to the bodies of NMOS transistors in the DRAM.
FIG. 1 is a schematic of a conventional two-stage charge pump circuit 100 that generates a pumped output voltage V.sub.P having an amplitude greater than the amplitude of a supply voltage source V.sub.CC in response to complementary clock signals CLK and CLK, as will be described in more detail below. The charge pump circuit 100 includes two voltage-boosting stages 102 and 104 connected in series between an input voltage node 106 and an output voltage node 108. The voltage-boosting stage 102 includes a capacitor 110 receiving the clock signal CLK on a first terminal and having a second terminal coupled to the input node 106. A diode-coupled transistor 112 is coupled between the input voltage node 106 and a voltage node 114, and operates as a unidirectional switch to transfer charge stored on the capacitor 110 to a capacitor 116 in the second voltage-boosting stage 104. The capacitor 116 receives the complementary clock signal CLK, and a diode-coupled transistor 118 operates as a unidirectional switch to transfer charge stored on the capacitor 116 to a load capacitor C.sub.L coupled between the output voltage node 108 and ground. A diode-coupled transistor 120 is coupled between the supply voltage source V.sub.CC and node 106, and operates as a unidirectional switch to transfer charge from the supply voltage source V.sub.CC to the capacitor 110. As understood by those skilled in the art, the clock signals CLK and CLK are complementary signals so there is a phase shift of 180.degree. between the clock signals.
The operation of the conventional charge pump circuit 100 of FIG. 1 will now be described in more detail with reference to the timing diagram of FIG. 2, which illustrates the voltages at various points in the charge pump circuit 100 during operation. At just before a time t.sub.0, the CLK signal is low having a voltage of approximately 0 volts and the CLK signal is high having a voltage of approximately the supply voltage V.sub.CC, and each of the voltages on the nodes 106, 114, and 108 have assumed values as shown for the sake of example. When the CLK signal is low, the terminal of the capacitor 110 is accordingly at approximately ground and the voltage at the node 106 of the diode-coupled transistor 120 is the threshold voltage V.sub.T less than the supply voltage V.sub.CC. As a result, the capacitor 110 is charged to V.sub.CC less V.sub.T. As shown in FIG. 2, the voltage at the node 106 (i.e., the voltage across the capacitor 110) is increasing just before the time to as the capacitor 110 is being charged. Also just before the time to, the voltage at the node 114 equals the high voltage of the CLK signal plus the voltage stored across the capacitor 116. This bootstrapped voltage on the node 114 is sufficiently greater than the voltage V.sub.P on the output voltage node 108 to turn ON the transistor 118, transferring charge from the capacitor 116 through the transistor 118 to charge the load capacitor C.sub.L. As shown, the voltage at node 114 is decreasing and the voltage V.sub.P increasing just before the time t.sub.0 as charge is being transferred through the transistor 118.
At the time to, the CLK signal goes high, driving the voltage on the node 106 to the high voltage (V.sub.CC) of the CLK signal plus the voltage stored across the capacitor 110 (V.sub.110). At this point, the voltage on the node 106 is sufficiently high to turn OFF the transistor 120 isolating the node 106 from the supply voltage source V.sub.CC. Also at the time to, the CLK signal goes low (to ground), causing the voltage on the node 114 to equal the voltage V.sub.116 stored across the capacitor 116. The voltage on the node 106 is now sufficiently greater than the voltage on the node 114 to turn ON the transistor 112, transferring charge from the capacitor 110 through the transistor 112 to the capacitor 116. As shown in FIG. 2, between the time t.sub.0 and a time t.sub.1, which corresponds to the interval the CLK signal is high and CLK signal is low, the voltage at the node 106 decreases and the voltage at the node 114 increases as charge is pumped or transferred through the transistor 112. It should be noted that during this time, the transistor 118 is turned OFF because the voltage V.sub.P is sufficiently greater than the voltage at the node 114 during normal operation of the charge pump circuit 100.
At the time t.sub.1, the CLK and CLK signals go low and high, respectively, and the charge pump circuit 100 operates in the same manner as previously described for just before the time t.sub.0. In other words, the transistor 112 turns OFF and transistors 118 and 120 turn ON, and charge is transferred from the supply voltage source V.sub.CC through the transistor 120 to the capacitor 110 and charge is transferred from the capacitor 116 through the transistor 118 to the load capacitor C.sub.L. As seen in FIG. 2, from the time t.sub.1, to a time t.sub.2 the voltage at the node 106 increases as the capacitor 110 is charging and the voltages on nodes 114 and 108 decrease and increase, respectively, as charge is transferred from the capacitor 116 to the load capacitor C.sub.L. At the time t.sub.2, the CLK and CLK signals again go high and low, respectively, and the charge pump circuit 100 operates as previously described at the time t.sub.0.
The charge pump circuit 100 continues operating in this manner, pumping charge from the supply voltage source V.sub.CC to the successive capacitors 110, 116, and C.sub.L to develop the desired pumped voltage V.sub.P across the capacitor C.sub.L. In the charge pump circuit 100, the maximum value of the voltage V.sub.P equals 3VCC-V.sub.T120 -V.sub.T112 -V.sub.T118 where the voltages V.sub.T120, V.sub.T112, and V.sub.T118 are the threshold voltages of the transistors 120, 112, and 118, respectively. Thus, the threshold voltages of these transistors reduce the voltage gain (V.sub.P /V.sub.CC) of the charge pump circuit 100. To alleviate this problem, more stages may be added to the charge pump circuit 100, but this increases the overall size, complexity, and power consumption of the circuit. Furthermore, in conventional charge pump circuits, as the amplitude of the pumped voltage V.sub.P increases the threshold voltages of the diode-coupled transistors in later stages increase due to the "body effect" of these MOS transistors. As understood by one skilled in the art, the body effect of a MOS transistor is the effect different source-to-substrate voltages have on the threshold voltage V.sub.T of the transistor. The body effect results in the threshold voltage V.sub.T of a MOS transistor increasing as the reverse bias voltage applied across the source-to-substrate junction increases in magnitude. In the charge pump circuit 100 of FIG. 1, the substrates for each of the transistors 120, 112, and 118 are typically coupled to ground. Thus, as the voltage increases on the successive sources of the transistors 120, 112, and 118, the respective threshold voltages V.sub.T120, V.sub.T112, and V.sub.T118 increase accordingly. For example, the voltage on the node 108 is greater than the voltage on the node 106, and thus the source-to-substrate voltage of the transistor 118 is greater than that of the transistor 120 and accordingly the threshold voltage V.sub.T118 of the transistor 118 will be greater than the threshold voltage V.sub.T120 of the transistor 120. The increased values for the threshold voltages V.sub.T of transistors in later stages of the charge pump circuit 100 reduce the voltage gain of the charge pump circuit.
The supply voltages of modem electronic devices are steadily decreasing in an effort to reduce the power consumption of such devices. As the amplitude of the supply voltage source V.sub.CC becomes smaller, the voltage gain of conventional charge pump circuits may be substantially decreased by the threshold voltages of the diode-coupled transistors, particularly by those transistors in later stages as previously described. In fact, as the amplitude of the supply voltage source V.sub.CC approaches the magnitude of the threshold voltages, no voltage gain may be possible since the diode-coupled transistors 120, 112, and 118 may never turn ON. For example, if V.sub.CC equals 1 volt and V.sub.T120 equals 1 volt, even when the node 106 is at ground the transistor 120 will not turn ON to charge the capacitor 110.
There is a need for a charge pump circuit having a relatively small number of voltage-boosting stages that generates a relatively large pumped output voltage from a low supply voltage.